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Question

Truth table for system of four NAND gates as shown in figure is :
40211_fbe098abf1f248be98b7b2ad24137dc3.png
  1. 40211_155178_c2f983db2c3c4006ad6fe9fdb68c67c0.png
  2. 40211_155179_65e8967732844212a5bab4ac026ce200.png
  3. 40211_155180_08bbce4c80e84c29bd22dd8822995f45.png
  4. 40211_155181_1479b66c3868447983f602ee0599c320.png

A
40211_155181_1479b66c3868447983f602ee0599c320.png
B
40211_155178_c2f983db2c3c4006ad6fe9fdb68c67c0.png
C
40211_155179_65e8967732844212a5bab4ac026ce200.png
D
40211_155180_08bbce4c80e84c29bd22dd8822995f45.png
Solution
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As shown in the logic diagram,
Output Y=¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯(A.¯¯¯¯¯¯¯¯¯¯¯A.B)¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯(B.¯¯¯¯¯¯¯¯¯¯¯¯¯A.B).....eq(1)

When A=0,B=0 putting A and B in eq (1) Y=0
When A=0,B=1 putting A and B in eq (1) Y=1
When A=1,B=0 putting A and B in eq (1) Y=1
When A=1,B=1 putting A and B in eq (1) Y=0
Hence option A is correct.

776148_40211_ans_2c6278397fd34bb1b9e09af32aac8451.png

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